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1/42 may 2005 m95320 m95320-w m95320-r m95320-s m95640 m95640-w m95640-r M95640-S 32kbit and 64kbit serial spi bus eeproms with high speed clock features summary compatible with spi bus serial interface (positive clock spi modes) single supply voltage: ? 4.5 to 5.5v for m95320 and m95640 ? 2.5 to 5.5v for m95320-w and m95320-w ? 1.8 to 5.5v for m95320-r and m95640-r ? 1.65 to 5.5v for m95320-s and M95640-S 20mhz, 10mhz, 5mhz or 2mhz clock rates 5ms or 10ms write time status register hardware protection of the status register byte and page write (up to 32 bytes) self-timed programming cycle adjustable size read-only eeprom area enhanced esd protection more than 100000 or 1 million erase/write cycles (depending on ordering options) more than 40-year data retention table 1. product list figure 1. packages reference part number m95320 m95320 m95320-w m95320-r m95320-s m95640 m95640 m95640-w m95640-r M95640-S 8 1 8 1 pdip8 (bn) 0.25 mm frame so8 (mn) 150 mil width tssop8 (dw) 169 mil width mlp8 (mb) 2x3 mm
m95640, m95320 2/42 table of contents features summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 1. product list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 figure 1. packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 table 2. how to identify previous, current and new products by the process identification letter 5 figure 2. logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 3. 8 pin package connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 table 3. signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 serial data output (q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 serial data input (d) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 serial clock (c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 chip select (s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 hold (hold) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 write protect (w) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 connecting to the spi bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 4. bus master and memory devices on the spi bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 spi modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 5. spi modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 operating features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 power on reset: vcc lock-out write protect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 active power and standby power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 hold condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 6. hold condition activation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 wip bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 wel bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 bp1, bp0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 srwd bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 4. status register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 data protection and protocol control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 5. write-protected block size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3/42 m95640, m95320 figure 7. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 6. instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 write enable (wren) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 8. write enable (wren) sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 write disable (wrdi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 9. write disable (wrdi) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 read status register (rdsr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 wip bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 wel bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 bp1, bp0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 srwd bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 10.read status register (rdsr) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 write status register (wrsr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 7. protection modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 8. address range bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 11.write status register (wrsr) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 read from memory array (read) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 12.read from memory array (read) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 write to memory array (write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 figure 13.byte write (write) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 14.page write (write) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 power-up and delivery state. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1 power-up state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 initial delivery state. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 maximum rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 9. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 dc and ac parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 10. operating conditions (m95320 and m95640) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 11. operating conditions (m95320-w and m95640-w) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 12. operating conditions (m95320-r and m95640-r) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 13. operating conditions (m95320-s and M95640-S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 14. ac measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 15.ac measurement i/o waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 15. capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 16. dc characteristics (m95320 and m95640, device grade 6) . . . . . . . . . . . . . . . . . . . . . 24 table 17. dc characteristics (m95320 and m95640, device grade 3) . . . . . . . . . . . . . . . . . . . . . 25 table 18. dc characteristics (m95320-w and m95640-w, device grade 6) . . . . . . . . . . . . . . . . . 26 table 19. dc characteristics (m95320-w and m95640-w, device grade 3) . . . . . . . . . . . . . . . . . 27 table 20. dc characteristics (m95320-r and m95640-r) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 21. dc characteristics (m95320-s and M95640-S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
m95640, m95320 4/42 table 22. ac characteristics (m95320 and m95640, device grade 6). . . . . . . . . . . . . . . . . . . . . . 28 table 23. ac characteristics (m95320 and m95640, device grade 3). . . . . . . . . . . . . . . . . . . . . . 29 table 24. ac characteristics (m95320-w and m95640-w, device grade 6) . . . . . . . . . . . . . . . . . 30 table 25. ac characteristics (m95320-w and m95640-w, device grade 3) . . . . . . . . . . . . . . . . . 31 table 26. ac characteristics (m95320-r and m95640-r) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 27. ac characteristics (m95320-s and M95640-S, device grade 3) . . . . . . . . . . . . . . . . . . 33 figure 16.serial input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 17.hold timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 18.output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 19.pdip8 ? 8 pin plastic dip, 0.25mm lead frame, package outline . . . . . . . . . . . . . . . . . 36 table 28. pdip8 ? 8 pin plastic dip, 0.25mm lead frame, package mechanical data . . . . . . . . . . 36 figure 20.so8 narrow ? 8 lead plastic small outline, 150 mils body width, package outline . . . . 37 table 29. so8 narrow ? 8 lead plastic small outline, 150 mils body width, package mechanical data 37 figure 21.tssop8 ? 8 lead thin shrink small outline, package outline . . . . . . . . . . . . . . . . . . . 38 table 30. tssop8 ? 8 lead thin shrink small outline, package mechanical data . . . . . . . . . . . . 38 figure 22.mlp8 - 8-lead ultra thin fine pitch dual flat no lead, package outline . . . . . . . . . . . . 39 table 31. mlp8 - 8-lead ultra thin fine pitch dual flat no lead, package mechanical data . . . . 39 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 32. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 0 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 33. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
5/42 m95640, m95320 summary description these electrically erasable programmable memo- ry (eeprom) devices are accessed by a high speed spi-compatible bus. the m95320, m95320-w, m95320-r and m95320-s are 32kbit devices organized as 4096 x 8 bits. the m95640, m95640-w, m95640-r and M95640-S are 64kbit devices organized as 8192 x 8 bits. the device is accessed by a simple serial interface that is spi-compatible. the bus signals are c, d and q, as shown in table 3. and figure 2. . the device is selected when chip select (s ) is tak- en low. communications with the device can be interrupted using hold (hold ). the devices are available in three different ver- sions identified by a specific marking (see table 2. ). table 2. how to identify previous, current and new products by the process identification letter note: 1. for further information, please ask your st sales office for process change notices. figure 2. logic diagram figure 3. 8 pin package connections note: 1. see package mechanical section for package di- mensions and how to identify pin-1. 2. nc, not connected. table 3. signal names devices root part numbers markings on previous products 1 markings on current products 1 markings on new products 1 m95320, m95640, m95320-w, m95640-w device grade 6 xxxx s xxxx v xxxx p m95320, m95640, m95320-w, m95640-w device grade 3 xxxx s xxxx b xxxx p m95320-r, m95640-r - - xxxx p m95320-s, M95640-S - - xxxx p ai01789c s v cc m95xxx hold v ss w q c d c serial clock d serial data input q serial data output s chip select w write protect hold hold v cc supply voltage v ss ground d v ss c hold q sv cc w ai01790d m95xxx 1 2 3 4 8 7 6 5
m95640, m95320 6/42 signal description during all operations, v cc must be held stable and within the specified valid range: v cc (min) to v cc (max). all of the input and output signals must be held high or low (according to voltages of v ih , v oh , v il or v ol , as specified in table 16. to table 20. ). these signals are described next. serial data output (q). this output signal is used to transfer data serially out of the device. data is shifted out on the falling edge of serial clock (c). serial data input (d). this input signal is used to transfer data serially into the device. it receives in- structions, addresses, and the data to be written. values are latched on the rising edge of serial clock (c). serial clock (c). this input signal provides the timing of the serial interface. instructions, address- es, or data present at serial data input (d) are latched on the rising edge of serial clock (c). data on serial data output (q) changes after the falling edge of serial clock (c). chip select (s ). when this input signal is high, the device is deselected and serial data output (q) is at high impedance. unless an internal write cycle is in progress, the device will be in the stand- by power mode. driving chip select (s ) low se- lects the device, placing it in the active power mode. after power-up, a falling edge on chip select (s ) is required prior to the start of any instruction. hold (hold ). the hold (hold ) signal is used to pause any serial communications with the device without deselecting the device. during the hold condition, the serial data output (q) is high impedance, and serial data input (d) and serial clock (c) are don?t care. to start the hold condition, the device must be se- lected, with chip select (s ) driven low. write protect (w ). the main purpose of this in- put signal is to freeze the size of the area of mem- ory that is protected against write instructions (as specified by the values in the bp1 and bp0 bits of the status register). this pin must be driven either high or low, and must be stable during all write operations.
7/42 m95640, m95320 connecting to the spi bus these devices are fully compatible with the spi protocol. all instructions, addresses and input data bytes are shifted in to the device, most significant bit first. the serial data input (d) is sampled on the first rising edge of the serial clock (c) after chip select (s ) goes low. all output data bytes are shifted out of the device, most significant bit first. the serial data output (q) is latched on the first falling edge of the serial clock (c) after the instruction (such as the read from memory array and read status register in- structions) have been clocked into the device. figure 4. shows three devices, connected to an mcu, on a spi bus. only one device is selected at a time, so only one device drives the serial data output (q) line at a time, all the others being high impedance. figure 4. bus master and memory devices on the spi bus note: the write protect (w ) and hold (hold ) signals should be driven, high or low as appropriate. ai03746e bus master (st6, st7, st9, st10, others) spi memory device sdo sdi sck cqd s spi memory device cqd s spi memory device cqd s cs3 cs2 cs1 spi interface with (cpol, cpha) = (0, 0) or (1, 1) w hold w hold w hold rrr v cc v cc v cc v cc
m95640, m95320 8/42 spi modes these devices can be driven by a microcontroller with its spi peripheral running in either of the two following modes: ? cpol=0, cpha=0 ? cpol=1, cpha=1 for these two modes, input data is latched in on the rising edge of serial clock (c), and output data is available from the falling edge of serial clock (c). the difference between the two modes, as shown in figure 5. , is the clock polarity when the bus master is in stand-by mode and not transferring data: ? c remains at 0 for (cpol=0, cpha=0) ? c remains at 1 for (cpol=1, cpha=1) figure 5. spi modes supported ai01438b c msb cpha d 0 1 cpol 0 1 q c msb
9/42 m95640, m95320 operating features power-up when the power supply is turned on, v cc rises from v ss to v cc . during this time, the chip select (s ) must be al- lowed to follow the v cc voltage. it must not be al- lowed to float, but should be connected to v cc via a suitable pull-up resistor. as a built in safety feature, chip select (s ) is edge sensitive as well as level sensitive. after power- up, the device does not become selected until a falling edge has first been detected on chip select (s ). this ensures that chip select (s ) must have been high, prior to going low to start the first op- eration. power on reset: v cc lock-out write protect in order to prevent inadvertent write operations during power-up, each device include a power on reset (por) circuit. at power-up, the device will not respond to any instruction until v cc has reached the power on reset threshold voltage. this threshold is lower than the v cc min operating voltage defined in tables 10 , 11 , 12 and 13 . similarly, as soon as v cc drops from the normal operating voltage, below the power on reset threshold voltage, the device stops responding to any instruction sent to it. prior to selecting and issuing instructions to the memory, a valid stable v cc voltage must be ap- plied. this voltage must remain stable and valid until the end of the transmission of the instruction and, for a write instruction, until the completion o the internal write cycle (t w ). power-down at power-down, the device must be deselected. chip select (s ) should be allowed to follow the voltage applied on v cc . active power and standby power modes when chip select (s ) is low, the device is select- ed, and in the active power mode. the device consumes i cc , as specified in table 16. to table 20. . when chip select (s ) is high, the device is dese- lected. if an erase/write cycle is not currently in progress, the device then goes in to the standby power mode, and the device consumption drops to i cc1 . hold condition the hold (hold ) signal is used to pause any se- rial communications with the device without reset- ting the clocking sequence. during the hold condition, the serial data output (q) is high impedance, and serial data input (d) and serial clock (c) are don?t care. to enter the hold condition, the device must be selected, with chip select (s ) low. normally, the device is kept selected, for the whole duration of the hold condition. deselecting the de- vice while it is in the hold condition, has the effect of resetting the state of the device, and this mech- anism can be used if it is required to reset any pro- cesses that had been in progress. the hold condition starts when the hold (hold ) signal is driven low at the same time as serial clock (c) already being low (as shown in figure 6. ). the hold condition ends when the hold (hold ) signal is driven high at the same time as serial clock (c) already being low. figure 6. also shows what happens if the rising and falling edges are not timed to coincide with serial clock (c) being low.
m95640, m95320 10/42 figure 6. hold condition activation status register figure 7. shows the position of the status register in the control logic of the device. the status reg- ister contains a number of status and control bits that can be read or set (as appropriate) by specific instructions. wip bit. the write in progress (wip) bit indicates whether the memory is busy with a write or write status register cycle. wel bit. the write enable latch (wel) bit indi- cates the status of the internal write enable latch. bp1, bp0 bits. the block protect (bp1, bp0) bits are non-volatile. they define the size of the area to be software protected against write instructions. srwd bit. the status register write disable (srwd) bit is operated in conjunction with the write protect (w ) signal. the status register write disable (srwd) bit and write protect (w ) signal allow the device to be put in the hardware protected mode. in this mode, the non-volatile bits of the status register (srwd, bp1, bp0) become read-only bits. table 4. status register format data protection and protocol control non-volatile memory devices can be used in envi- ronments that are particularly noisy, and within ap- plications that could experience problems if memory bytes are corrupted. consequently, the device features the following data protection mechanisms: write and write status register instructions are checked that they consist of a number of clock pulses that is a multiple of eight, before they are accepted for execution. all instructions that modify data must be preceded by a write enable (wren) instruction to set the write enable latch (wel) bit. this bit is returned to its reset state by the following events: ? power-up ? write disable (wrdi) instruction completion ? write status register (wrsr) instruction completion ? write (write) instruction completion the block protect (bp1, bp0) bits allow part of the memory to be configured as read-only. this is the software protected mode (spm). the write protect (w ) signal allows the block protect (bp1, bp0) bits to be protected. this is the hardware protected mode (hpm). for any instruction to be accepted, and executed, chip select (s ) must be driven high after the rising edge of serial clock (c) for the last bit of the in- struction, and before the next rising edge of serial clock (c). two points need to be noted in the previous sen- tence: ai02029d hold c hold condition hold condition b7 b0 srwd 0 0 0 bp1 bp0 wel wip status register write protect block protect bits write enable latch bit write in progress bit
11/42 m95640, m95320 ? the ?last bit of the instruction? can be the eighth bit of the instruction code, or the eighth bit of a data byte, depending on the instruction (except for read status register (rdsr) and read (read) instructions). ? the ?next rising edge of serial clock (c)? might (or might not) be the next bus transaction for some other device on the spi bus. table 5. write-protected block size status register bits protected block array addresses protected bp1 bp0 m95640, m95640-w, m95640-r, M95640-S m95320, m95320-w, m95320-r, m95320-s 0 0 none none none 0 1 upper quarter 1800h - 1fffh 0c00h - 0fffh 1 0 upper half 1000h - 1fffh 0800h - 0fffh 1 1 whole memory 0000h - 1fffh 0000h - 0fffh
m95640, m95320 12/42 memory organization the memory is organized as shown in figure 7. . figure 7. block diagram ai01272c hold s w control logic high voltage generator i/o shift register address register and counter data register 1 page x decoder y decoder c d q size of the read only eeprom area status register
13/42 m95640, m95320 instructions each instruction starts with a single-byte code, as summarized in table 6. . if an invalid instruction is sent (one not contained in table 6. ), the device automatically deselects it- self. table 6. instruction set instruc tion description instruction format wren write enable 0000 0110 wrdi write disable 0000 0100 rdsr read status register 0000 0101 wrsr write status register 0000 0001 read read from memory array 0000 0011 write write to memory array 0000 0010
m95640, m95320 14/42 write enable (wren) the write enable latch (wel) bit must be set pri- or to each write and wrsr instruction. the only way to do this is to send a write enable instruction to the device. as shown in figure 8. , to send this instruction to the device, chip select (s ) is driven low, and the bits of the instruction byte are shifted in, on serial data input (d). the device then enters a wait state. it waits for a the device to be deselected, by chip select (s ) being driven high. figure 8. write enable (wren) sequence write disable (wrdi) one way of resetting the write enable latch (wel) bit is to send a write disable instruction to the device. as shown in figure 9. , to send this instruction to the device, chip select (s ) is driven low, and the bits of the instruction byte are shifted in, on serial data input (d). the device then enters a wait state. it waits for a the device to be deselected, by chip select (s ) be- ing driven high. the write enable latch (wel) bit, in fact, be- comes reset by any of the following events: ? power-up ? wrdi instruction execution ? wrsr instruction completion ? write instruction completion. figure 9. write disable (wrdi) sequence c d ai02281e s q 2 1 34567 high impedance 0 instruction c d ai03750d s q 2 1 34567 high impedance 0 instruction
15/42 m95640, m95320 read status register (rdsr) the read status register (rdsr) instruction al- lows the status register to be read. the status register may be read at any time, even while a write or write status register cycle is in progress. when one of these cycles is in progress, it is rec- ommended to check the write in progress (wip) bit before sending a new instruction to the device. it is also possible to read the status register con- tinuously, as shown in figure 10. . the status and control bits of the status register are as follows: wip bit. the write in progress (wip) bit indicates whether the memory is busy with a write or write status register cycle. when set to 1, such a cycle is in progress, when reset to 0 no such cycle is in progress. wel bit. the write enable latch (wel) bit indi- cates the status of the internal write enable latch. when set to 1 the internal write enable latch is set, when set to 0 the internal write enable latch is reset and no write or write status register in- struction is accepted. bp1, bp0 bits. the block protect (bp1, bp0) bits are non-volatile. they define the size of the area to be software protected against write instructions. these bits are written with the write status regis- ter (wrsr) instruction. when one or both of the block protect (bp1, bp0) bits is set to 1, the rele- vant memory area (as defined in table 4. ) be- comes protected against write (write) instructions. the block protect (bp1, bp0) bits can be written provided that the hardware protect- ed mode has not been set. srwd bit. the status register write disable (srwd) bit is operated in conjunction with the write protect (w ) signal. the status register write disable (srwd) bit and write protect (w ) signal allow the device to be put in the hardware protected mode (when the status register write disable (srwd) bit is set to 1, and write protect (w ) is driven low). in this mode, the non-volatile bits of the status register (srwd, bp1, bp0) be- come read-only bits and the write status register (wrsr) instruction is no longer accepted for exe- cution. figure 10. read status register (rdsr) sequence c d s 2 1 3456789101112131415 instruction 0 ai02031e q 7 6543210 status register out high impedance msb 7 6543210 status register out msb 7
m95640, m95320 16/42 write status register (wrsr) the write status register (wrsr) instruction al- lows new values to be written to the status regis- ter. before it can be accepted, a write enable (wren) instruction must previously have been ex- ecuted. after the write enable (wren) instruction has been decoded and executed, the device sets the write enable latch (wel). the write status register (wrsr) instruction is entered by driving chip select (s ) low, followed by the instruction code and the data byte on serial data input (d). the instruction sequence is shown in figure 11. . the write status register (wrsr) instruction has no effect on b6, b5, b4, b1 and b0 of the status register. b6, b5 and b4 are always read as 0. chip select (s ) must be driven high after the rising edge of serial clock (c) that latches in the eighth bit of the data byte, and before the next rising edge of serial clock (c). otherwise, the write status register (wrsr) instruction is not executed. as soon as chip select (s ) is driven high, the self- timed write status register cycle (whose duration is t w ) is initiated. while the write status register cycle is in progress, the status register may still be read to check the value of the write in progress (wip) bit. the write in progress (wip) bit is 1 dur- ing the self-timed write status register cycle, and is 0 when it is completed. when the cycle is com- pleted, the write enable latch (wel) is reset. the write status register (wrsr) instruction al- lows the user to change the values of the block protect (bp1, bp0) bits, to define the size of the area that is to be treated as read-only, as defined in table 4. . the write status register (wrsr) instruction also allows the user to set or reset the status register write disable (srwd) bit in accordance with the write protect (w ) signal. the status register write disable (srwd) bit and write protect (w ) signal allow the device to be put in the hardware protected mode (hpm). the write status register (wrsr) instruction is not executed once the hard- ware protected mode (hpm) is entered. the contents of the status register write disable (srwd) and block protect (bp1, bp0) bits are fro- zen at their current values from just before the start of the execution of write status register (wrsr) instruction. the new, updated, values take effect at the moment of completion of the ex- ecution of write status register (wrsr) instruc- tion. table 7. protection modes note: 1. as defined by the values in the block protect (bp1, bp0) bits of the status register, as shown in table 5. . the protection features of the device are summa- rized in table 5. . when the status register write disable (srwd) bit of the status register is 0 (its initial delivery state), it is possible to write to the status register provided that the write enable latch (wel) bit has previously been set by a write enable (wren) in- struction, regardless of the whether write protect (w ) is driven high or low. when the status register write disable (srwd) bit of the status register is set to 1, two cases need to be considered, depending on the state of write protect (w ): ? if write protect (w ) is driven high, it is possible to write to the status register provided that the write enable latch (wel) bit has previously been set by a write enable (wren) instruction. ? if write protect (w ) is driven low, it is not possible to write to the status register even if the write enable latch (wel) bit has previously been set by a write enable (wren) instruction. (attempts to write to the status register are rejected, and are not accepted for execution). as a consequence, all the data bytes in the memory area that are software protected (spm) by the block protect w signal srwd bit mode write protection of the status register memory content protected area 1 unprotected area 1 10 software protected (spm) status register is writable (if the wren instruction has set the wel bit) the values in the bp1 and bp0 bits can be changed write protected ready to accept write instructions 00 11 01 hardware protected (hpm) status register is hardware write protected the values in the bp1 and bp0 bits cannot be changed write protected ready to accept write instructions
17/42 m95640, m95320 (bp1, bp0) bits of the status register, are also hardware protected against data modification. regardless of the order of the two events, the hardware protected mode (hpm) can be entered: ? by setting the status register write disable (srwd) bit after driving write protect (w ) low ? or by driving write protect (w ) low after setting the status register write disable (srwd) bit. the only way to exit the hardware protected mode (hpm) once entered is to pull write protect (w ) high. if write protect (w ) is permanently tied high, the hardware protected mode (hpm) can never be activated, and only the software protected mode (spm), using the block protect (bp1, bp0) bits of the status register, can be used. table 8. address range bits note: b15 to b13 are don?t care on the 64 kbit devices. b15 to b12 are don?t care on the 32 kbit devices. figure 11. write status register (wrsr) sequence device 32 kbit devices 64 kbit devices address bits a12-a0 a11-a0 c d ai02282d s q 2 1 3456789101112131415 high impedance instruction status register in 0 765432 0 1 msb
m95640, m95320 18/42 read from memory array (read) as shown in figure 12. , to send this instruction to the device, chip select (s ) is first driven low. the bits of the instruction byte and address bytes are then shifted in, on serial data input (d). the ad- dress is loaded into an internal address register, and the byte of data at that address is shifted out, on serial data output (q). if chip select (s ) continues to be driven low, the internal address register is automatically incre- mented, and the byte of data at the new address is shifted out. when the highest address is reached, the address counter rolls over to zero, allowing the read cycle to be continued indefinitely. the whole memory can, therefore, be read with a single read instruc- tion. the read cycle is terminated by driving chip se- lect (s ) high. the rising edge of the chip select (s ) signal can occur at any time during the cycle. the first byte addressed can be any byte within any page. the instruction is not accepted, and is not execut- ed, if a write cycle is currently in progress. figure 12. read from memory array (read) sequence note: depending on the memory size, as shown in table 8. , the most significant address bits are don?t care. c d ai01793d s q 15 2 1 345678910 2021222324252627 1413 3210 28 29 30 76543 1 7 0 high impedance data out 1 instruction 16-bit address 0 msb msb 2 31 data out 2
19/42 m95640, m95320 write to memory array (write) as shown in figure 13. , to send this instruction to the device, chip select (s ) is first driven low. the bits of the instruction byte, address byte, and at least one data byte are then shifted in, on serial data input (d). the instruction is terminated by driving chip se- lect (s ) high at a byte boundary of the input data. in the case of figure 13. , this occurs after the eighth bit of the data byte has been latched in, in- dicating that the instruction is being used to write a single byte. the self-timed write cycle starts, and continues for a period t wc (as specified in ta- ble 22. to table 26. ), at the end of which the write in progress (wip) bit is reset to 0. if, though, chip select (s ) continues to be driven low, as shown in figure 14. , the next byte of input data is shifted in, so that more than a single byte, starting from the given address towards the end of the same page, can be written in a single internal write cycle. each time a new data byte is shifted in, the least significant bits of the internal address counter are incremented. if the number of data bytes sent to the device exceeds the page boundary, the inter- nal address counter rolls over to the beginning of the page, and the previous data there are overwrit- ten with the incoming data. (the page size of these devices is 32 bytes). the instruction is not accepted, and is not execut- ed, under the following conditions: ? if the write enable latch (wel) bit has not been set to 1 (by executing a write enable instruction just before) ? if a write cycle is already in progress ? if the device has not been deselected, by chip select (s ) being driven high, at a byte boundary (after the eighth bit, b0, of the last data byte that has been latched in) ? if the addressed page is in the region protected by the block protect (bp1 and bp0) bits. figure 13. byte write (write) sequence note: depending on the memory size, as shown in table 8. , the most significant address bits are don?t care. c d ai01795d s q 15 2 1 345678910 2021222324252627 1413 3210 28 29 30 high impedance instruction 16-bit address 0 765432 0 1 data byte 31
m95640, m95320 20/42 figure 14. page write (write) sequence note: depending on the memory size, as shown in table 8. , the most significant address bits are don?t care. c d ai01796d s 34 33 35 36 37 38 39 40 41 42 44 45 46 47 32 c d s 15 2 1 345678910 2021222324252627 1413 3210 28 29 30 instruction 16-bit address 0 765432 0 1 data byte 1 31 43 765432 0 1 data byte 2 765432 0 1 data byte 3 65432 0 1 data byte n
21/42 m95640, m95320 power-up and delivery state power-up state after power-up, the device is in the following state: ? standby power mode ? deselected (after power-up, a falling edge is required on chip select (s ) before any instructions can be started). ? not in the hold condition ? the write enable latch (wel) is reset to 0 ? write in progress (wip) is reset to 0 the srwd, bp1 and bp0 bits of the status reg- ister are unchanged from the previous power- down (they are non-volatile bits). initial delivery state the device is delivered with the memory array set at all 1s (ffh). the status register write disable (srwd) and block protect (bp1 and bp0) bits are initialized to 0.
m95640, m95320 22/42 maximum rating stressing the device outside the ratings listed in table 9. may cause permanent damage to the de- vice. these are stress ratings only, and operation of the device at these, or any other conditions out- side those indicated in the operating sections of this specification, is not implied. exposure to ab- solute maximum rating conditions for extended periods may affect device reliability. refer also to the stmicroelectronics sure program and other relevant quality documents. table 9. absolute maximum ratings note: 1. compliant with jedec std j-std-020c (for small body, sn-pb or pb assembly), the st ecopack ? 7191395 specification, and the european directive on restrictions on hazardous substances (rohs) 2002/95/eu 2. aec-q100-002 (compliant with jedec std jesd22-a114a, c1=100pf, r1=1500 ? , r2=500 ? ) symbol parameter min. max. unit t stg storage temperature ?65 150 c t lead lead temperature during soldering see note 1 c v o output voltage ?0.50 v cc +0.6 v v i input voltage ?0.50 6.5 v v cc supply voltage ?0.50 6.5 v v esd electrostatic discharge voltage (human body model) 2 ?4000 4000 v
23/42 m95640, m95320 dc and ac parameters this section summarizes the operating and mea- surement conditions, and the dc and ac charac- teristics of the device. the parameters in the dc and ac characteristic tables that follow are de- rived from tests performed under the measure- ment conditions summarized in the relevant tables. designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parame- ters. table 10. operating conditions (m95320 and m95640) table 11. operating conditions (m95320-w and m95640-w) table 12. operating conditions (m95320-r and m95640-r) note: 1. this product is under development. for more information, please contact your nearest st sales office. table 13. operating conditions (m95320-s and M95640-S) note: 1. this product is under development. for more information, please contact your nearest st sales office. table 14. ac measurement conditions note: output hi-z is defined as the point where data out is no longer driven. symbol parameter min. max. unit v cc supply voltage 4.5 5.5 v t a ambient operating temperature (device grade 6) ?40 85 c ambient operating temperature (device grade 3) ?40 125 c symbol parameter min. max. unit v cc supply voltage 2.5 5.5 v t a ambient operating temperature (device grade 6) ?40 85 c ambient operating temperature (device grade 3) ?40 125 c symbol parameter min. 1 max. 1 unit v cc supply voltage 1.8 5.5 v t a ambient operating temperature ?40 85 c symbol parameter min. 1 max. 1 unit v cc supply voltage 1.65 5.5 v t a ambient operating temperature ?40 85 c symbol parameter min. typ. max. unit c l load capacitance 30 pf input rise and fall times 50 ns input pulse voltages 0.2v cc to 0.8v cc v input and output timing reference voltages 0.3v cc to 0.7v cc v
m95640, m95320 24/42 figure 15. ac measurement i/o waveform table 15. capacitance note: sampled only, not 100% tested, at t a =25c and a frequency of 5mhz. table 16. dc characteristics (m95320 and m95640, device grade 6) note: 1. for all 5v range devices, the device meets the output requirements for both ttl and cmos standards. 2. previous product version is identified by process identification letter ?s?. 3. current product version is identified by process identification letter ?v??. 4. new product version is identified by process identification letter ?p?. 5. preliminary data. symbol parameter test condition min . max . unit c out output capacitance (q) v out = 0v 8 pf c in input capacitance (d) v in = 0v 8 pf input capacitance (other pins) v in = 0v 6 pf symbol parameter test condition min. max. unit i li input leakage current v in = v ss or v cc 2 a i lo output leakage current s = v cc , v out = v ss or v cc 2 a i cc supply current c = 0.1v cc /0.9v cc at 5mhz, v cc = 5v, q = open, previous product 2 4ma c=0.1v cc /0.9v cc at 10mhz, v cc = 5v, q = open, current product 3 5ma c=0.1v cc /0.9v cc at 20mhz, v cc = 5v, q = open, new product 4,5 10 ma i cc1 supply current (standby) s = v cc , v cc = 5v, v in = v ss or v cc , previous product 2 10 a s = v cc , v cc = 5v, v in = v ss or v cc , current product 3 2a s = v cc , v cc = 5v, v in = v ss or v cc , new product 4,5 2a v il input low voltage ?0.45 0.3 v cc v v ih input high voltage 0.7 v cc v cc +1 v v ol 1 output low voltage i ol = 2 ma, v cc = 5v 0.4 v v oh 1 output high voltage i oh = ?2 ma, v cc = 5v 0.8 v cc v ai00825b 0.8v cc 0.2v cc 0.7v cc 0.3v cc input and output timing reference levels input levels
25/42 m95640, m95320 table 17. dc characteristics (m95320 and m95640, device grade 3) note: 1. for all 5v range devices, the device meets the output requirements for both ttl and cmos standards. 2. previous product version is identified by process identification letter ?s?. 3. current product version is identified by process identification letters ?b?. 4. new product version is identified by process identification letters ?p?. 5. preliminary data. symbol parameter test condition min. max. unit i li input leakage current v in = v ss or v cc 2 a i lo output leakage current s = v cc , v out = v ss or v cc 2 a i cc supply current c = 0.1v cc /0.9v cc at 2mhz, v cc = 5v, q = open, previous product 2 2ma c = 0.1v cc /0.9v cc at 5mhz, v cc = 5v, q = open, current product 3 4ma c=0.1v cc /0.9v cc at 20mhz, v cc = 5v, q = open, new product 4,5 12 ma i cc1 supply current (standby) s = v cc , v cc = 5v, v in = v ss or v cc , previous product 2 20 a s = v cc , v cc = 5v, v in = v ss or v cc , current product 3 5a s = v cc , v cc = 5v, v in = v ss or v cc , new product 4,5 2a v il input low voltage ?0.45 0.3 v cc v v ih input high voltage 0.7 v cc v cc +1 v v ol 1 output low voltage i ol = 2ma, v cc = 5v 0.4 v v oh 1 output high voltage i oh = ?2ma, v cc = 5v 0.8 v cc v
m95640, m95320 26/42 table 18. dc characteristics (m95320-w and m95640-w, device grade 6) note: 1. previous product version is identified by process identification letter ?s?. 2. current product version is identified by process identification letter ?v??. 3. new product version is identified by process identification letter ?p?. 4. preliminary data. table 19. dc characteristics (m95320-w and m95640-w, device grade 3) note: 1. current product version is identified by process identification letter ?b?. 2. new product version is identified by process identification letter ?p?. symbol parameter test condition min. max. unit i li input leakage current v in = v ss or v cc 2 a i lo output leakage current s = v cc , v out = v ss or v cc 2 a i cc supply current c = 0.1v cc /0.9v cc at 2mhz, v cc = 2.5v, q = open, previous product 1 2ma c = 0.1v cc /0.9v cc at 5mhz, v cc = 2.5v, q = open, current product 2 3ma c=0.1v cc /0.9v cc at 10mhz, v cc = 2.5v, q = open, new product 3,4 5 ma i cc1 supply current (standby) s = v cc , v cc = 2.5v, v in = v ss or v cc , previous product 1 2a s = v cc , v cc = 2.5v v in = v ss or v cc , current product 2 1a s = v cc , v cc = 2.5v v in = v ss or v cc , new product 3,4 1 a v il input low voltage ?0.45 0.3 v cc v v ih input high voltage 0.7 v cc v cc +1 v v ol output low voltage i ol = 1.5ma, v cc = 2.5v 0.4 v v oh output high voltage i oh = ?0.4ma, v cc = 2.5v 0.8 v cc v symbol parameter test condition min. max. unit i li input leakage current v in = v ss or v cc 2 a i lo output leakage current s = v cc , v out = v ss or v cc 2 a i cc supply current c = 0.1v cc /0.9v cc at 5mhz, v cc = 2.5v, q = open, current product 1 3ma c=0.1v cc /0.9v cc at 10mhz, v cc = 2.5v, q = open, new product 2 6ma i cc1 supply current (standby) s = v cc , v cc = 2.5v, v in = v ss or v cc 2a v il input low voltage ?0.45 0.3 v cc v v ih input high voltage 0.7 v cc v cc +1 v v ol output low voltage i ol = 1.5ma, v cc = 2.5v 0.4 v v oh output high voltage i oh = ?0.4ma, v cc = 2.5v 0.8 v cc v
27/42 m95640, m95320 table 20. dc characteristics (m95320-r and m95640-r) note: 1. this product is under qualification. for more information, please contact your nearest st sales office. 2. preliminary data. table 21. dc characteristics (m95320-s and M95640-S) note: 1. this product is under qualification. for more information, please contact your nearest st sales office. 2. preliminary data. symbol parameter test condition min. 1,2 max. 1,2 unit i li input leakage current v in = v ss or v cc 1 a i lo output leakage current s = v cc , v out = v ss or v cc 1 a i cc supply current c = 0.1v cc /0.9v cc at 5mhz, v cc = 1.8 v, q = open 3ma i cc1 supply current (standby) s = v cc , v in = v ss or v cc , v cc = 1.8v 1a v il input low voltage ?0.45 0.3 v cc v v ih input high voltage 0.7 v cc v cc +1 v v ol output low voltage i ol = 0.15 ma, v cc = 1.8 v 0.3 v v oh output high voltage i oh = ?0.1 ma, v cc = 1.8 v 0.8 v cc v symbol parameter test condition min. 1,2 max. 1,2 unit i li input leakage current v in = v ss or v cc 1 a i lo output leakage current s = v cc , v out = v ss or v cc 1 a i cc supply current c = 0.1v cc /0.9v cc at 2mhz, v cc = 1.65 v, q = open 1ma i cc1 supply current (standby) s = v cc , v in = v ss or v cc , v cc = 1.65v 1a v il input low voltage ?0.45 0.3 v cc v v ih input high voltage 0.7 v cc v cc +1 v v ol output low voltage i ol = 0.15 ma, v cc = 1.65v 0.3 v v oh output high voltage i oh = ?0.1 ma, v cc = 1.65v 0.8 v cc v
m95640, m95320 28/42 table 22. ac characteristics (m95320 and m95640, device grade 6) note: 1. t ch + t cl must never be lower than the shortest possible clock period, 1/f c (max). 2. value guaranteed by characterization, not 100% tested in production. 3. previous product version is identified by process identification letter ?s?. 4. current product version is identified by process identification letter ?v??. 5. new product version is identified by process identification letter ?p?. 6. preliminary data. test conditions specified in table 14. and table 10. symbol alt. parameter previous product version 3 current product version 4 new product version 5,6 unit min. max. min. max. min. max. f c f sck clock frequency d.c. 5 d.c. 10 d.c. 20 mhz t slch t css1 s active setup time 90 15 15 ns t shch t css2 s not active setup time 90 15 15 ns t shsl t cs s deselect time 100 40 20 ns t chsh t csh s active hold time 90 25 15 ns t chsl s not active hold time 90 15 15 ns t ch 1 t clh clock high time 90 40 20 ns t cl 1 t cll clock low time 90 40 20 ns t clch 2 t rc clock rise time 1 1 2 s t chcl 2 t fc clock fall time 1 1 2 s t dvch t dsu data in setup time 20 15 5 ns t chdx t dh data in hold time 30 15 10 ns t hhch clock low hold time after hold not active 70 15 15 ns t hlch clock low hold time after hold active 40 20 15 ns t clhl clock low set-up time before hold active 0 0 0 ns t clhh clock low set-up time before hold not active 000ns t shqz 2 t dis output disable time 100 25 20 ns t clqv t v clock low to output valid 60 25 20 ns t clqx t ho output hold time 0 0 0 ns t qlqh 2 t ro output rise time 50 20 20 ns t qhql 2 t fo output fall time 50 20 20 ns t hhqv t lz hold high to output valid 50 25 20 ns t hlqz 2 t hz hold low to output high-z 100 25 20 ns t w t wc write time 10 5 5 ms
29/42 m95640, m95320 table 23. ac characteristics (m95320 and m95640, device grade 3) note: 1. t ch + t cl must never be lower than the shortest possible clock period, 1/f c (max). 2. value guaranteed by characterization, not 100% tested in production. 3. previous product version is identified by process identification letter ?s?. 4. current product version is identified by process identification letter ?b?. 5. new product version is identified by process identification letter ?p?. 6. preliminary data. test conditions specified in table 14. and table 10. symbol alt. parameter previous product version 3 current product version 4 new product version 5,6 unit min. max. min. max. min. max. f c f sck clock frequency d.c. 2 d.c. 5 d.c. 20 mhz t slch t css1 s active setup time 200 90 15 ns t shch t css2 s not active setup time 200 90 15 ns t shsl t cs s deselect time 200 100 20 ns t chsh t csh s active hold time 200 90 15 ns t chsl s not active hold time 200 90 15 ns t ch 1 t clh clock high time 200 90 20 ns t cl 1 t cll clock low time 200 90 20 ns t clch 2 t rc clock rise time 1 1 2 s t chcl 2 t fc clock fall time 1 1 2 s t dvch t dsu data in setup time 40 20 5 ns t chdx t dh data in hold time 50 30 10 ns t hhch clock low hold time after hold not active 140 70 15 ns t hlch clock low hold time after hold active 90 40 15 ns t clhl clock low set-up time before hold active 0 0 0 ns t clhh clock low set-up time before hold not active 00 0ns t shqz 2 t dis output disable time 250 100 20 ns t clqv t v clock low to output valid 150 60 20 ns t clqx t ho output hold time 0 0 0 ns t qlqh 2 t ro output rise time 100 50 20 ns t qhql 2 t fo output fall time 100 50 20 ns t hhqv t lz hold high to output valid 100 50 20 ns t hlqz 2 t hz hold low to output high-z 250 100 20 ns t w t wc write time 10 5 5 ms
m95640, m95320 30/42 table 24. ac characteristics (m95320-w and m95640-w, device grade 6) note: 1. t ch + t cl must never be lower than the shortest possible clock period, 1/f c (max). 2. value guaranteed by characterization, not 100% tested in production. 3. previous product version is identified by process identification letter ?s?. 4. current product version is identified by process identification letter ?v??. 5. new product version is identified by process identification letter ?p?. 6. preliminary data. test conditions specified in table 14. and table 11. symbol alt. parameter previous product version 3 current product version 4 new product version 5,6 unit min. max. min. max. min. max. f c f sck clock frequency d.c. 2 d.c. 5 d.c. 10 mhz t slch t css1 s active setup time 200 90 30 ns t shch t css2 s not active setup time 200 90 30 ns t shsl t cs s deselect time 200 100 40 ns t chsh t csh s active hold time 200 90 30 ns t chsl s not active hold time 200 90 30 ns t ch 1 t clh clock high time 200 90 40 ns t cl 1 t cll clock low time 200 90 40 ns t clch 2 t rc clock rise time 1 1 2 s t chcl 2 t fc clock fall time 1 1 2 s t dvch t dsu data in setup time 40 20 10 ns t chdx t dh data in hold time 50 30 10 ns t hhch clock low hold time after hold not active 140 70 30 ns t hlch clock low hold time after hold active 90 40 30 ns t clhl clock low set-up time before hold active 0 0 0 ns t clhh clock low set-up time before hold not active 000ns t shqz 2 t dis output disable time 250 100 40 ns t clqv t v clock low to output valid 150 60 40 ns t clqx t ho output hold time 0 0 0 ns t qlqh 2 t ro output rise time 100 50 40 ns t qhql 2 t fo output fall time 100 50 40 ns t hhqv t lz hold high to output valid 100 50 40 ns t hlqz 2 t hz hold low to output high-z 250 100 40 ns t w t wc write time 10 5 5 ms
31/42 m95640, m95320 table 25. ac characteristics (m95320-w and m95640-w, device grade 3) note: 1. t ch + t cl must never be lower than the shortest possible clock period, 1/f c (max). 2. value guaranteed by characterization, not 100% tested in production. 3. current product version is identified by process identification letter ?v??. 4. new product version is identified by process identification letter ?p?. 5. preliminary data. test conditions specified in table 14. and table 11. symbol alt. parameter current product version 3 new product version 4,5 unit min. max. min. max. f c f sck clock frequency d.c. 5 d.c. 10 mhz t slch t css1 s active setup time 90 30 ns t shch t css2 s not active setup time 90 30 ns t shsl t cs s deselect time 100 40 ns t chsh t csh s active hold time 90 30 ns t chsl s not active hold time 90 30 ns t ch 1 t clh clock high time 90 40 ns t cl 1 t cll clock low time 90 40 ns t clch 2 t rc clock rise time 1 2 s t chcl 2 t fc clock fall time 1 2 s t dvch t dsu data in setup time 20 10 ns t chdx t dh data in hold time 30 10 ns t hhch clock low hold time after hold not active 70 30 ns t hlch clock low hold time after hold active 40 30 ns t clhl clock low set-up time before hold active 0 0ns t clhh clock low set-up time before hold not active 0 0 ns t shqz 2 t dis output disable time 100 40 ns t clqv t v clock low to output valid 60 40 ns t clqx t ho output hold time 0 0 ns t qlqh 2 t ro output rise time 50 40 ns t qhql 2 t fo output fall time 50 40 ns t hhqv t lz hold high to output valid 50 40 ns t hlqz 2 t hz hold low to output high-z 100 40 ns t w t wc write time 5 5 ms
m95640, m95320 32/42 table 26. ac characteristics (m95320-r and m95640-r) note: 1. t ch + t cl must never be lower than the shortest possible clock period, 1/f c (max). 2. value guaranteed by characterization, not 100% tested in production. 3. preliminary data: this product is under qualification. for more information, please contact your nearest st sales office. 4. new product version is identified by process identification letter ?p?. test conditions specified in table 14. and table 12. symbol alt. parameter min. 3,4 max. 3,4 unit f c f sck clock frequency d.c. 5 mhz t slch t css1 s active setup time 60 ns t shch t css2 s not active setup time 60 ns t shsl t cs s deselect time 90 ns t chsh t csh s active hold time 60 ns t chsl s not active hold time 60 ns t ch 1 t clh clock high time 90 ns t cl 1 t cll clock low time 90 ns t clch 2 t rc clock rise time 2 s t chcl 2 t fc clock fall time 2 s t dvch t dsu data in setup time 20 ns t chdx t dh data in hold time 20 ns t hhch clock low hold time after hold not active 60 ns t hlch clock low hold time after hold active 60 ns t clhl clock low set-up time before hold active 0 0 t clhh clock low set-up time before hold not active 0 0 t shqz 2 t dis output disable time 80 ns t clqv t v clock low to output valid 80 ns t clqx t ho output hold time 0 ns t qlqh 2 t ro output rise time 80 ns t qhql 2 t fo output fall time 80 ns t hhqv t lz hold high to output valid 80 ns t hlqz 2 t hz hold low to output high-z 80 ns t w t wc write time 5 ms
33/42 m95640, m95320 table 27. ac characteristics (m95320-s device grade 3) note: 1. t ch + t cl must never be lower than the shortest possible clock period, 1/f c (max). 2. value guaranteed by characterization, not 100% tested in production. 3. preliminary data: this product is under qualification. for more information, please contact your nearest st sales office. 4. new product version is identified by process identification letter ?p?. test conditions specified in table 14. and table 12. symbol alt. parameter min. 3,4 max. 3,4 unit f c f sck clock frequency d.c. 2 mhz t slch t css1 s active setup time 150 ns t shch t css2 s not active setup time 150 ns t shsl t cs s deselect time 200 ns t chsh t csh s active hold time 150 ns t chsl s not active hold time 150 ns t ch 1 t clh clock high time 200 ns t cl 1 t cll clock low time 200 ns t clch 2 t rc clock rise time 2 s t chcl 2 t fc clock fall time 2 s t dvch t dsu data in setup time 50 ns t chdx t dh data in hold time 50 ns t hhch clock low hold time after hold not active 150 ns t hlch clock low hold time after hold active 150 ns t clhl clock low set-up time before hold active 0 0 t clhh clock low set-up time before hold not active 0 0 t shqz 2 t dis output disable time 200 ns t clqv t v clock low to output valid 200 ns t clqx t ho output hold time 0 ns t qlqh 2 t ro output rise time 200 ns t qhql 2 t fo output fall time 200 ns t hhqv t lz hold high to output valid 200 ns t hlqz 2 t hz hold low to output high-z 200 ns t w t wc write time 10 ms
m95640, m95320 34/42 figure 16. serial input timing figure 17. hold timing c d ai01447c s msb in q tdvch high impedance lsb in tslch tchdx tchcl tclch tshch tshsl tchsh tchsl c q ai01448b s d hold tclhl thlch thhch tclhh thhqv thlqz
35/42 m95640, m95320 figure 18. output timing c q ai01449d s lsb out d addr.lsb in tshqz tch tcl tqlqh tqhql tclqx tclqv tclqx tclqv
m95640, m95320 36/42 package mechanical figure 19. pdip8 ? 8 pin plastic dip, 0.25mm lead frame, package outline note: drawing is not to scale. table 28. pdip8 ? 8 pin plastic dip, 0.25mm lead frame, package mechanical data symb. mm inches typ. min. max. typ. min. max. a5.330.210 a1 0.38 0.015 a2 3.30 2.92 4.95 0.130 0.115 0.195 b 0.46 0.36 0.56 0.018 0.014 0.022 b2 1.52 1.14 1.78 0.060 0.045 0.070 c 0.25 0.20 0.36 0.010 0.008 0.014 d 9.27 9.02 10.16 0.365 0.355 0.400 e 7.87 7.62 8.26 0.310 0.300 0.325 e1 6.35 6.10 7.11 0.250 0.240 0.280 e 2.54 ? ? 0.100 ? ? ea 7.62 ? ? 0.300 ? ? eb 10.92 0.430 l 3.30 2.92 3.81 0.130 0.115 0.150 pdip-b a2 a1 a l be d e1 8 1 c ea b2 eb e
37/42 m95640, m95320 figure 20. so8 narrow ? 8 lead plastic small outline, 150 mils body width, package outline note: drawing is not to scale. table 29. so8 narrow ? 8 lead plastic small out line, 150 mils body width, package mechanical data symb. mm inches typ. min. max. typ. min. max. a 1.35 1.75 0.053 0.069 a1 0.10 0.25 0.004 0.010 b 0.33 0.51 0.013 0.020 c 0.19 0.25 0.007 0.010 d 4.80 5.00 0.189 0.197 e 3.80 4.00 0.150 0.157 e 1.27 ? ? 0.050 ? ? h 5.80 6.20 0.228 0.244 h 0.25 0.50 0.010 0.020 l 0.40 0.90 0.016 0.035 0 8 0 8 n8 8 cp 0.10 0.004 so-a e n cp b e a d c l a1 1 h h x 45?
m95640, m95320 38/42 figure 21. tssop8 ? 8 lead thin shrink small outline, package outline note: drawing is not to scale. table 30. tssop8 ? 8 lead thin shrink small outline, package mechanical data symbol mm inches typ. min. max. typ. min. max. a 1.200 0.0472 a1 0.050 0.150 0.0020 0.0059 a2 1.000 0.800 1.050 0.0394 0.0315 0.0413 b 0.190 0.300 0.0075 0.0118 c 0.090 0.200 0.0035 0.0079 cp 0.100 0.0039 d 3.000 2.900 3.100 0.1181 0.1142 0.1220 e 0.650 ? ? 0.0256 ? ? e 6.400 6.200 6.600 0.2520 0.2441 0.2598 e1 4.400 4.300 4.500 0.1732 0.1693 0.1772 l 0.600 0.450 0.750 0.0236 0.0177 0.0295 l1 1.000 0.0394 0 8 0 8 tssop8am 1 8 cp c l e e1 d a2 a e b 4 5 a1 l1
39/42 m95640, m95320 figure 22. mlp8 - 8-lead ultra thin fine pitch dual flat no lead, package outline note: drawing is not to scale. table 31. mlp8 - 8-lead ultra thin fine pitch dual flat no lead, package mechanical data symbol millimeters inches typ min max typ min max a 0.55 0.50 0.60 0.022 0.020 0.024 a1 0.00 0.05 0.000 0.002 b 0.25 0.20 0.30 0.010 0.008 0.012 d 2.00 0.079 d2 1.55 1.65 0.061 0.065 ddd 0.05 0.002 e 3.00 0.118 e2 0.15 0.25 0.006 0.010 e 0.50 ? ? 0.020 ? ? l 0.45 0.40 0.50 0.018 0.016 0.020 l1 0.15 0.006 l3 0.30 0.012 n8 8 d e ufdfpn-01 a a1 ddd l1 e b d2 l e2 l3
m95640, m95320 40/42 part numbering table 32. ordering information scheme note: 1. st strongly recommends the use of the automotive grade devices for use in an automotive environment. the high reliabilit y cer- tified flow (hrcf) is described in the quality note qnee9801. please ask your nearest st sales office for a copy. 2. devices bearing the process identification letter ?b? or ?v? in the package marking (on the top side of the package, on the r ight side), guarantee more than 1 million erase/write cycle endurance (see table 2. ). for more information about these devices, and their device identification, please contact your nearest st sales office, and ask for the product change notice. for a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest st sales office. example: m95640 ? w mn 6 t p device type m95 = spi serial access eeprom device function 2 640 = 64 kbit (8192 x 8) 320 = 32 kbit (4096 x 8) operating voltage blank = v cc = 4.5 to 5.5v w = v cc = 2.5 to 5.5v r = v cc = 1.8 to 5.5v s = v cc = 1.65 to 5.5v package bn = pdip8 mn = so8 (150 mil width) dw = tssop8 (169 mil width) mb = mlp8 (2x3 mm) device grade 6 = industrial temperature range, ?40 to 85 c. device tested with standard test flow 3 = device tested with high reliability certified flow 1 . automotive temperature range (?40 to 125 c) option blank = standard packing t = tape and reel packing plating technology blank = standard snpb plating p or g = lead-free and rohs compliant
41/42 m95640, m95320 revision history table 33. document revision history date rev. description of revision 13-jul-2000 1.2 human body model meets jedec std (table 2). minor adjustments on pp 1,11,15. new clause on p7. addition of tssop8 package on pp 1, 2, ordering info, mechanical data 16-mar-2001 1.3 test condition added i li and i lo , and specification of t dldh and t dhdl removed. t clch , t chcl , t dldh and t dhdl changed to 50ns for the -v range. ?-v? voltage range changed to ?2.7v to 3.6v? throughout. maximum lead soldering time and temperature conditions updated. instruction sequence illustrations updated. ?bus master and memory devices on the spi bus? illustration updated. package mechanical data updated 19-jul-2001 1.4 m95160 and m95080 devices removed to their own data sheet 06-dec-2001 1.5 endurance increased to 1m write/erase cycles instruction sequence illustrations updated 18-dec-2001 2.0 document reformatted using the new template. no parameters changed. 08-feb-2002 2.1 announcement made of planned upgrade to 10mhz clock for the 5v, ?40 to 85c, range. endurance set to 100k write/erase cycles 18-dec-2002 2.2 10mhz, 5mhz, 2mhz clock; 5ms, 10ms write time; 100k, 1m erase/write cycles distinguished on front page, and in the dc and ac characteristics tables 26-mar-2003 2.3 process indentification letter corrected in footnote to ac characteristics table for temp. range 3 26-jun-2003 2.4 -s voltage range upgraded by removing it and inserting -r voltage range in its place 15-oct-2003 3.0 table of contents, and pb-free options added. v il (min) improved to -0.45v 21-nov-2003 3.1 v i (min) and v o (min) corrected (improved) to -0.45v 28-jan-2004 4.0 tssop8 connections added to dip and so connections 24-may-2005 5.0 m95320-s and M95640-S root part numbers (1.65 to 5.5v supply) and related characteristics added. 20mhz clock rate added.tssop14 package removed and mlp8 package added. description of power on reset: vcc lock-out write protect updated. product list summary table added. absolute maximum ratings for v io (min) and v cc (min) improved. soldering temperature information clarified for rohs compliant devices. device grade 3 clarified, with reference to hrcf and automotive environments. aec-q100-002 compliance. t chhl (min) and t chhh (min) is t ch for products under ?s? process. t hhqx corrected to t hhqv . figure 17., hold timing updated.
m95640, m95320 42/42 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replac es all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners ? 2005 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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